Junior Digital Design/Verification Engineer 结束招聘
- 工作地点 上海 北京
- 所属行业 --
- 薪资待遇 查看薪资
- 发布日期 2020年10月13日
- 职位详情 Junior Digital Design/Verification Engineer
- 截止日期 2021年07月31日
- 招聘人数 若干人
职位描述及要求
Job Description:
- Successful candidate will be responsible for the digital design or verification tasks in state-of-the art ASICs & SoCs for mixed signal products such as Audio Codec or VSM (Vital Signal Monitoring). Candidate will work with the application and design team to establish the digital specifications; participate in the design / integration / implementation or verification of the building blocks (such as MCU, DSP, signal-chain, bus-matrix, peripherals, clock and power management, customized digital features, etc.).
Job Requirements:
- Solid knowledge of industry standard digital design methodology
- Experienced Verilog coder
- Knowledge of UVM, system-Verilog is a plus
- Knowledge about analog building block behavior modeling is a plus. The building blocks includes OPA, ADC, DAC, PLL,Comparator etc.
- Knowledge about signal processing and CPU architecture is a plus
- Experience in verifying complex digital design using UVM is a plus.
- Experience with different types of verifications such as RTL, gates, regression is a plus
- Experience in verifying mixed-signal design is a plus.
- Scripting skills with Matlab, Perl, and Python for design and verification modeling is a plus
- Strong inter-personal, teamwork and communication skills are required.
- Self-motivated, Result oriented.
- Good English
- Master’s degree in EE or related area